This invention relates to the field of charge coupled device memories used for the temporary storage and repeated accessing of analog data.
In the processing of weak signals received from a low-level energy source such as a radio frequency or optical radiator there is need for small size relatively low cost temporary storage of analog signal data and for repeated accessing of this data. This storage and repeated accessing allow, for example, cancellation of random noise signal components and reinforcing-addition enhancement of the desired signal components. One technique for accomplishing this type of storage involves charge transfer devices of the bucket brigade or charge coupled device (CCD) type, the CCD is, for example, particularly attractive for storage used in the canonic recursive filters employed in radar signal processing. Signal processing arrangements of this type are identified as post-detection integration processors. CCD storage is also useful in embodying signal filters.
One arrangement for achieving CCD storage of such signal information would be, of course, to provide a long serial register and to fill this register with analog values representing received signals during a sample interval. In circulating analog signal values around a long serial CCD register at high clocking rates and for numerous recirculation times, however, a problem of signal degradation is found to exist. In a CCD memory this signal degradation is to a large degree attributable to charge transfer inefficiency, a lack of complete charge transfer between the wells comprising individual CCD storage locations. Following a number of transfer events between CCD wells an original signal is therefore found to be diminished in signal-to-noise ratio and eventually subject to becoming lost.
Several techniques have been developed for maintaining the integrity of a signal circulated around a charge coupled device closed-loop memory array, one of these techniques, the additive refresh concept was proposed in the paper "Low Loss CCD Concept" presented by the Fifth International Conference on CCDs, Edinburg Scotland, Sept 1979, pp. 432-437, by W. F. Kosonocky and D. J. Sauer and is employed in the present invention apparatus. The contents of the Kosonocky and Sauer paper are hereby incorporated by reference into the present specification. In addition to additive refresh signal maintenance it is also found desirable in a CCD circulating memory array to minimize the number of serial transfers of data between CCD wells since serial transfers, especially at high speed, are a major source of signal degradation. A reduction in the number of serial transfers occurring therefore reduces the amount of signal degradation and the corresponding signal enhancement that is required in a particular CCD system.
The classic approach to limiting the number of serial transfers required in a memory of given size involves use of a combination of serial operated and parallel operated memory stages in an apparatus which has become known as a serial-parallel-serial (SPS) memory. In such memories, data may be received from a serially-operating input, assembled in a register and then transferred out of the assembly register in parallel form for propagation through a succession or stack of slower operating parallel stages. The final register in the parallel stack is also capable of serial operation and is employed in such serial operation to place the parallel propagated memory data once again in serial form. An SPS memory is commonly referred to dimensionally as having M parallel columns of N vertically stacked stages. In this arrangement the total number of storage sites is (M.multidot.N), however, in achieving a delay of length M.multidot.N, the data need transfer only through M+N stages. The greatest saving in number of signal transfers in an SPS memory occurs for square arrays (M=N), however, other factors such as clock drive considerations enter into an array configuration tradeoff.
An SPS organized memory offers another benefit relating to sample-to-sample isolation. This benefit can be appreciated by realizing that the data behind a particular signal sample is a second sample during signal storage in the fast horizontal register of an SPS combination, but is a completely different third signal sample during transit through the slow SPS column registers. Thus, in contrast to a purely serial memory, crosstalk in an SPS memory is split between two different sets of signal samples. Each signal sample therefore receives less crosstalk in an SPS memory than would be the case in a purely serial memory of the same size. As the number of cells in each direction of an SPS memory is varied, of course, the crosstalk for each of the signals varies in response to the number of charge transfers in each direction and the effective charge transfer efficiency for each such transfer.
SPS memory arrangements are known in the patent art, as is illustrated by the patent of Ramesh C. Varshney et al, U.S. Pat. No. 4,165,541, which discloses a serial-parallel-serial charge coupled device memory of the bi-directional type wherein each serial section is both an input register and an output register and wherein serial streams of charge packets flow simultaneously in opposite directions in the parallel section. In the Varshney patent, odd data bits of a serial input stream flow into a first serial register, through a parallel section in a first direction, and then out of the second serial register, while concurrently even data bits flow into the second serial register, then through the parallel section in the opposite or second direction and thence out of the first serial register. This arrangement provides a substantially increased data transfer rate and is identified as an interlace and ripple clock arrangement. The Varshney patent also includes an informative discussion of prior art attending charge coupled device SPS memories.
Another example of SPS CCD memories is found in the patent of James B. Barton, U.S. Pat. No. 3,914,748, which concerns a CCD analog array arranged to minimize dispersion and crosstalk problems through the use of isolation element charge packets and also through the use of a multiplexed pair of shift registers.
An example of serial-parallel-loop charge coupled device circuitry is found in the patent of George S. Leach, Jr., U.S. Pat. No. 4,206,370, which discloses a CCD register apparatus employing loops of conductor material formed in an integrated circuit chip for the purpose of coupling signal between CCD cells and also employing different clock phases for CCD cells located in each loop.
Another SPS CCD apparatus is shown in the patent of John J. Byrne, U.S. Pat. No. 4,376,897, which discloses an unusual arrangement for transferring data between the last parallel shift register in a stack and the serial output register without requiring use of the mid-level fixed voltage required previously.
Another example of a serial-parallel-serial shift register arrangement is shown in the patent of Edwin B. Councill, U.S. Pat. No. 4,225,947, which concerns a serial-parallel-serial storage array having the capability of line accessing data in the parallel storage registers for improved speed of data accessing and other advantages. The Councill apparatus also contemplates possible recirculation of the output from a single serial-parallel-serial memory array back to its input for continuous data retention.